AR# 37425: 12.3 EDK, 12.3 ISE - How do I create a custom AXI IP core?
12.3 EDK, 12.3 ISE - How do I create a custom AXI IP core?
How do I create a custom AXI IP core? The EDK Create IP Wizard does not have examples until EDK 13.1.
A collection of Verilog AXI4 master and an AXI4 slave, and VHDL AXI4-Stream master/slave example templates can be downloaded below.
Note that these currently only contain I/O port and parameter templates, except for Verilog AXI4 and AXI4-Lite master examples. Also, there isa VHDL AXI4-Stream loopback example available in (Xilinx Answer 38509). Further logic examples are to be added later. The EDK Create/Import Peripheral Wizard is to include AXI4/AXI4-Lite slave IPIF support in 13.1, and some master functionality in 13.2. For an example using the AXI_Lite_IPIF library for migration from PLB slave_single IPIF, see EDK AXI_GPIO.
For EDK designs, the AXI4 templates contain the MPD file parameters to configure a connected AXI Interconnect block. This includes services such as register pipelining, clock domain crossing, width conversion, and FIFOs. All examples are complete EDK pcores. To use, extract the above ".zip" file to a EDK project pcores/ directory, and choose Project->Rescan User Repositories. The cores are listed under USER in the IP Catalog.
For non-EDK designs, the HDL files from the axi_<corename>/hdl/verilog or axi_<corename>/hdl/vhdl directories can be used as an example HDL source.
AXI Design Tips:
When creating a design as an EDK pcore, there are multiple MPD parameters which are required to correctly parameterize the connected AXI_Interconnect, such as the data width. For example the following MHS parameter advertises to the AXI Interconnect that the M_AXI interface is 64 bits wide, and the interconnect will allocate appropriate logic for it: