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AR# 37434

Xilinx PlanAhead Solution Center -Errors and Warnings while running DRC's during Floorplanning


This portion of the Design Assistant will assist you with resolving errors and warnings that you receive when running DRCs while doing floorplanning within PlanAhead.

Note: This Answer Record is a part of the Xilinx PlanAhead Solution Center (Xilinx Answer 37100). The Xilinx PlanAhead Solution Center is available to address all questions related to PlanAhead. Whether you are starting a new design with PlanAhead or troubleshooting a problem, use the PlanAhead Solution Center to guide you to the right information.


See (Xilinx Answer 35743) for DRC error:

Error Messages :
BIVB Error Unsupported IOStandard in bank 1. For example, port mcb1_dram_ck (IOStd = DIFF_SSTL18_II) (IOStd = DIFF_SSTEL18_II) at site J17, M21.mcb1_dram_dqs
BIVB Error Unsupported IOStandard in bank 3. For example, port mcb3_dram_ck (IOStd = DIFF_SSTL18_II) (IOStd = DIFF_SSTEL18_II) at site F2, L3.mcb3_dram_dqs

See (Xilinx Answer 36372) for DRC error:

"DCI Cascade 25{I/O Bank 25, I/O Bank 26} has multiple DCI I/O standards in a "Split" termination type. Only one DCI I/O standard is allowed in a cascade. The following DCI I/O standards were found: 1. "SSTL15_T_DCI": c0_ddr3_dq[0] c0_ddr3_dq[1] 2. "DIFF_SSTL15_T_DCI": c0_ddr3_dqs_p[0] c0_ddr3_dqs_n[0] c0_ddr3_dqs_p[1] c0_ddr3_dqs_n[1] c0_ddr3_dqs_p[2]"

See (Xilinx Answer 35277) for DRC eror:

Regional clock terminal CLK_CC_AJ37 loced to site AJ37. There is no site for BUFR BUFR_3 reachable from AJ37

See (Xilinx Answer 33152)for DRC error:

DCM #1 clocking_I_clocks/CLKIN_IBUFG_INSTat F13 needs to be on the same edge as clocking_I_clocks/DCM_SP_INST @ DCM_X1Y3
F13 is adjacent to the DCM.

See (Xilinx Answer 35155) for DRC error:

"IOCNT #1 Fatal Design has more IOs (683) than placeable pins on the package (675)"

See (Xilinx Answer 31852)for DRC error:

"One or more Vr sites in bank I/O Bank occupied. Some terminals in this bank, for example terminals at sites need Vr"

See (Xilinx Answer 36814) for DRC error

DCM and BUFG connectivity -
DCM DCM_SP_INST placed at DCM_X1Y0 connects to BUFG CLK0_BUFG_INST placed at BUFGMUX_X1Y10. For correct operation both of them should be placed on the same edge.
Related Vios:

See (Xilinx Answer 35153) for DRC error:

"Conflicting Vcc voltages in bank I/O Bank 13. For example, the following two terminals locked to this bank have conflicting Vccs. Signal_X of IOStandard LVCMOS33 Vcc 3.3000 & Signal_Y of IOStandard LVCMOS25 Vcc 2.5000"

See (Xilinx Answer 31716) for DRC error:

"I/Os placed on prohibited sites"

See (Xilinx Answer 32471) for DRC error:

idelayctrl locked to bank 17 with no iodelay. sbuf_dq[33] at pin AE38 and others drive iodelays
AR# 37434
Date 12/15/2012
Status Archive
Type General Article
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