"> AR# 37460: PlanAhead Design Assistant - How do I get the most accuracy out of my PlanAhead Pin Planning DRCs?

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AR# 37460

PlanAhead Design Assistant - How do I get the most accuracy out of my PlanAhead Pin Planning DRCs?

Description

I want to ensure I catch as many DRC errors in my pin out in PlanAhead. How do I get the most accuracy out of PlanAhead's DRCs?

Note:This Answer Record is a part of the Xilinx PlanAhead Solution Center(Xilinx Answer 37100). The Xilinx PlanAhead Solution Center is available to address all questions related to the PlanAhead tool. Whether you are starting a new design with the PlanAhead toolor troubleshooting a problem, use the PlanAhead Solution Center to guide you to the right information.

Solution

Unless the netlist is present, there are some DRCs which the PlanAhead toolcannot run accurately. These are generally related to connectivity of the I/Os. For example, the PlanAhead tool will not know whether a pin is connected to a BUFG if the netlist is not present. Run DRCs on the Netlist Design for greatest accuracy.
AR# 37460
Date Created 08/19/2010
Last Updated 12/15/2012
Status Active
Type General Article