AR# 37497: Design Assistant for PCI Express - What should the Target Link Speed register in the Link Control 2 Register be set to?
Design Assistant for PCI Express - What should the Target Link Speed register in the Link Control 2 Register be set to?
What should the Target Link Speed register in the Link Control 2 Register be set to? NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.
The Target Link Speed register or bits 3:0 of the Link Control 2 register is used to set the upper limit of the link speed by restricting the values advertised by the upstream port's training sequences. For example, if the endpoint is capable of 5.0 GT/s, but the system would like to restrict this to 2.5 GT/s, it can write to this register to restrict the endpoint from advertising its 5.0 GT/s capable. The default value of this field is the highest Link Speed supported by the component as reported by the Supported Link Speed field of the Link Capabilities register. If the user selects that the core is to be 5.0 GT/s or Gen 2 capable during core customization, this value will default to 0010b for 5.0 GT/s, but the user has the option to change this during customization to be 0001b for 2.0 GT/s. If the user selects that the core is to be 2.5 GT/s or Gen 1 capableduring core customization, this value is set to 0000b as permitted by the specification. For a full description of this register, see section 7.8.19 of the PCI Base Specification v2.0 or later.