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AR# 37553

SPI-4.2 v10.1 - Certain Spartan-6 devices do not have enough pins in half banks for source core TX LVDS outputs

Description


The TX outputs for the source core require 18 pairs of LVDS outputs that use OSERDES with clocks driven by BUFIO2's.

The problem is that the Spartan-6 devices only have LVDS drivers available in banks 0 and 2 (see UG381, page 28).

In banks 0 and 2, the LX75T does not have 18 pairs of I/O pins (36 total) in the same half of the bank.

Each BUFIO2 only spans one half of a bank.

The OSERDES are in the netlist, so it is not possible to drive the sysclk to BUFIO2s on both halves of the bank and feed these to the OSERDES.
 
This is also an issue for other Spartan-6 devices and packages.

Solution

In the next version of the SPI-4.2 core, the Sink and Source will have split I/O clocking enable placement of the SPI-4.2 sink/source interface in one or two half banks.

The source interface will only be able to be placed in bank 2.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35109 SPI-4.2 v10.1 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 37553
Date Created 09/24/2010
Last Updated 09/08/2014
Status Active
Type General Article
Devices
  • Spartan-6 LXT
IP
  • SPI-4 Phase 2 Interface Solutions