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AR# 37591

Aurora 64b/66b - No USER_CLK for TX-only Simplex core

Description

TX-only Simplex Aurora 64B66B core should use GTX_TX_CLK_SOURCE as TXPLL.

Solution

The TX-only Simplex Aurora 64B66B core should use GTX_TX_CLK_SOURCE as "TXPLL". For a TX-only Simplex design, the GT should use TXPLL to lock the PLL in GT.

Modify the following parameter defined in <user_component_name>/example_design/gt/<user_component_name>_wrapper.v[hd]

For Verilog designs, look for "<user_component_name>_GTX" Instance & set the parameter as:

.GTX_TX_CLK_SOURCE ("TXPLL")

For VHDL designs, look for "<user_component_name>_GTX_INST" Instance & set the generic map as:

GTX_TX_CLK_SOURCE => "TXPLL",

A CR has been filed on the coreand will be reviewed during the next release of the core.
AR# 37591
Date Created 08/23/2010
Last Updated 01/24/2013
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-7
IP
  • Aurora 64B/66B