The current PCI specification requires a latency timer to be implemented within the core, which will insure bus ownership for a minimum amount of time for each master.
The latency timer is measured in units of PCI clocks. Its typical values are 32 and 64 clocks (1 and 2 microseconds). The timer starts when FRAME# is asserted, and it stops when the count expires OR FRAME# is de-asserted.
The master must vacate the bus when the latency timer has expired AND GNT# is de-asserted.