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AR# 37659

Spartan-6 FPGA GTP Transceiver Wizard - Implementing updated line rates in ISE Design Suite 12.2 and earlier

Description

This Answer Record discusses how to implement the updated line rates for the Spartan-6 FPGA GTP Transceiver in the Spartan-6 FPGA GTP Transceiver Wizard. The Spartan-6 FPGA Data Sheet (v1.9) (DS162) has updated the supported line rate ranges from 0.6 to 0.81; 1.2 to 1.62; and 2.4 to 3.125Gb/s seen in previous data sheets to 0.6 to 0.81; 0.94 to 1.62; and 1.88 to 3.2Gb/s.

Solution


There are two deviations from the standard Wizard generation flow that need to be taken note of to generate a wrapper for newly supported line rates:

1) In the Spartan-6 FPGA GTP Transceiver Wizard itself, when selecting a line rate, selectthe closest line rate from the previously supported range; note the proportion between the target line rate and that selected, and select a reference clock rate that is proportionally similar to the intended reference clock.This ensures that all the settings generated by the Wizard are correct for the resulting line rate, including the PLL divider settings.
2) The example UCF generated by the Wizardhastiming constraints that are incorrect for the target speeds. Update the reference clock period constraint to match the period of the expected reference clock, and the TX/RXUSRCLK(2) constraints to be in line with the formulas in the FPGA RX and TX Interface sections of the Spartan-6 FPGA GTP Transceiver User's Guide (UG386):
http://www.xilinx.com/support/documentation/user_guides/ug386.pdf

NOTE: In 12.2 and earlier, the speed files have not been updated to allow for line rates above 3.125Gb/s. Users that require higher line ratesneed to use 12.3 once it is released.
AR# 37659
Date Created 08/26/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
IP
  • Spartan-6 FPGA GTP Transceiver Wizard