We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37695

Virtex-6 - IDELAYCTRL Usage and Design Guidelines


In the Virtex-6FPGA SelectIO Resources User Guide (v1.3 and earlier) theIDELAYCTRL Usage and Design Guidelines section says:
"For more information on placing and locking IDELAYCTRLs, see the constraints guide under IODELAY_GROUP."


The IDELAYCTRL for the Virtex-6 is the same as the Virtex-5 (except some Virtex-6 IDELAYCTRLs can handle 300 MHz ref clk).
The recommended usage is to instantiate one IDELAYCTRL and to create IODELAY_GROUP constraints to allow automatic replication and placement. The user must create an IODELAY_GROUP for each bank that uses the IODELAY in FIXED or VARIABLE mode and the tools will replicate an IDELAYCTRL for each group. See the Constraints Guide for the syntax for the IODELAY_GROUP constraint.
AR# 37695
Date 02/05/2013
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Page Bookmarked