AR# 37710

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Virtex-6 FPGA Design Assistant - Board Level Considerations

Description


This section of the Virtex-6 FPGA Design Assistant focuses on getting started with the Virtex-6 FPGA. Select from the options below to find information related to your specific question.
NOTE: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963). The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices.Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.

Solution


Power
For information on power estimation, optimization, and system design, see the Power Solutions page:
http://www.xilinx.com/products/design_resources/power_central/
Configuration
For information on configuration solutions and debugging, see the Configuration Solutions Center:
http://www.xilinx.com/support/answers/34904.htm
Signal Integrity
For Signal Integrity considerations and information, see the Signal Integrity page:
http://www.xilinx.com/products/design_resources/signal_integrity/
Packaging
For packaging requirements, see the Virtex-6 FPGA Packaging and Pinout Specifications(UG365):
http://www.xilinx.com/support/documentation/user_guides/ug365.pdf
AR# 37710
Date 12/15/2012
Status Archive
Type General Article
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