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AR# 37747

14.7 XST - How do I define Verilog macros in XST and Project Navigator?


How do I define Verilog macros in XST and Project Navigator?


There are several ways to define macro or use include file for XST in Project Navigator.

  • Use the -define option in XST command line mode.
  • Place the values inside {braces). Separate each macro with spaces.

    Example: -define {WIDE=16 DEPTH=1024 DEBUG_CODE}

  • Use Verilog macros (-define) property in Synthesis Properties in Project Navigator.
  • Do not use {braces}. Use the pipe ( | ) symbol to separate each macro.

    Example: WIDE=16 | DEPTH=1024 | DEBUG_CODE

  • Define macros in one file, and use 'include for sources which need these definitions.
  • When an 'include statement references a file, XST searches for the file in the following order:

    1. Present working directory.
    2. -vlgincdir option of XST.
    3. Current file location that has 'include. (In this method make sure compile order is set correctly if there are different macro definitions for different files.)
  • Set the macro define file as one Global file in Compile List. Thus you need not use 'include in source file.
  • Right-click the macro define file, and choose Source Properties. And then check "Include as Global file in Compile List".

AR# 37747
Date 02/14/2014
Status Active
Type General Article
  • ISE Design Suite
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