"> AR# 37759: How Do I Use The Xilflash library With the Platform Flash XL on an ML605 board?

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AR# 37759

How Do I Use The Xilflash library With the Platform Flash XL on an ML605 board?

Description

On the ML605 board,the Linear BPI Flash shares the dual use configuration pins in parallel with the XCF128
Platform Flash XL. The block Diagram for the Platform Flash and the BPI flash can be seenbelow:

Platform Flash and the BPI flash

Here you can see there are two signalsand a switchthat select the Platform Flash, P30_CS_SEL and FPGA_FCS_B.
The switch is SW2.1, See page 57 of theML605 Hardware User Guidefor information on the SW2. Also, according the Platform Flash XL User Guide, page 23, for FPGA designs that access the Platform Flash XL, drive L# (latch)to a constant Low to enable thePlatform Flash XLaddress latch in asynchronous read/write operations.

To the the Xilflash library, there is examplesource code for thePlatform Flash Library in the EDK install directory:
<XILINX_EDK>\sw\lib\sw_services\xilflash_v2_02_a\examples\xilflash_platform_flash_example.c

Solution

To set up the hardware, create a simple BSB design for the ML605, choosing the Flash. This will use the XPS_MCH_EMC core
to connect the FLASH to the embedded system. Once the Project is created, remove theUTIL core and manually add
the signals to the MHS file mentioned above. The Platform Settings for the BSP are also seen below.

MHS File:
PORT fpga_0_FLASH_CE_inverter_Res_pin = net_gnd, DIR = O
PORT fpga_0_PLATFLASH_L_B_pin = net_gnd, DIR = O
PORT FPGA_FCS_B = net_bsbassign0, DIR = O


BEGIN xps_mch_emc
PARAMETER INSTANCE = FLASH
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CHANNELS = 0
PARAMETER C_MEM0_WIDTH = 16
PARAMETER C_MAX_MEM_WIDTH = 16
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_TCEDV_PS_MEM_0 = 110000
PARAMETER C_TAVDV_PS_MEM_0 = 110000
PARAMETER C_THZCE_PS_MEM_0 = 35000
PARAMETER C_TWC_PS_MEM_0 = 11000
PARAMETER C_TWP_PS_MEM_0 = 70000
PARAMETER C_TLZWE_PS_MEM_0 = 35000
PARAMETER HW_VER = 3.01.a
PARAMETER C_MEM0_BASEADDR = 0x8c000000
PARAMETER C_MEM0_HIGHADDR = 0x8dffffff
BUS_INTERFACE SPLB = mb_plb
PORT RdClk = clk_100_0000MHzMMCM0
PORT Mem_A = 0b0000000 & fpga_0_FLASH_Mem_A_pin_vslice_7_30_concat & 0b0
PORT Mem_CEN = net_bsbassign0
PORT Mem_OEN = fpga_0_FLASH_Mem_OEN_pin
PORT Mem_WEN = fpga_0_FLASH_Mem_WEN_pin
PORT Mem_DQ = fpga_0_FLASH_Mem_DQ_pin
END


UCF File:
Net fpga_0_FLASH_CE_inverter_Res_pin LOC=AJ12 | IOSTANDARD=LVCMOS25;
Net fpga_0_PLATFLASH_L_B_pin LOC=AC23 | IOSTANDARD=LVCMOS25;
Net FPGA_FCS_B LOC=Y24 | IOSTANDARD=LVCMOS25;



SDK BSP Configuration of the Xilflash Library:
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = xilflash
PARAMETER LIBRARY_VER = 2.01.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER NUM_PARTS = 1
PARAMETER BASE_ADDRESS = 0x8c000000
PARAMETER PLATFORM_FLASH = 1
END

AR# 37759
Date Created 01/23/2012
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 LXT
Tools
  • EDK - 12.3