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AR# 37784

Virtex-6 FPGA Integrated Block for PCI Express - x8 Gen 2 Timing Closure


Version Found: v2.1, v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 45723).

A TIG constraint and optional block RAM pipelining can be added to ease x8 Gen 2 timing closure.


Add the following constraints to the UCF file:

PIN "core/pcie_clocking_i/GEN2_LINK.pipe_clk_bufgmux.CE0" TIG;
PIN "core/pcie_clocking_i/GEN2_LINK.pipe_clk_bufgmux.CE1" TIG;

Also, enabling pipeline registers on the read and write side of the Transaction Block RAM can help timing closure.

To do this, on page 10 of the CORE Generator Customization GUI, select the option for "Buffer Write and Read".

Pipeline Registers for Transaction Block RAM Buffers = Buffer Write and Read.

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45723 Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions N/A N/A

Associated Answer Records

AR# 37784
Date 09/22/2014
Status Active
Type Known Issues
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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