UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37816

12.3 EDK - "ERROR:HDLCompiler:69 - "core_0_wrapper.v" Line 118: is not declared."

Description


I have imported an AXI interfaced IP core that I created and the following error occurs:
"ERROR:HDLCompiler:69 - "core_0_wrapper.v" Line 118: <AXI4> is not declared."
How do I work around this problem?

Solution


Browse to the data directory of your newly created pcore and open its MPD file.Find the line that contains the AXI4 (or a derivative of AXI4), and add the following to the end of the line:
, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
Save and close the file.
This problem is scheduled to be fixed in a future version of the EDK software.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34609 12.x EDK - Master Answer Record List N/A N/A
AR# 37816
Date Created 09/30/2010
Last Updated 05/20/2012
Status Active
Type Error Message
Tools
  • EDK - 12.3