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AR# 37831

10.1 EDK - DRC Error "C_SPLB0 has native width set to 32..." when using XPS TFT core

Description

I am using Spartan-3E 1600E MicroBlaze Edition, and using EDK 10.1 service pack 3. When I try to connect mplb bus of the XPS TFT IP interface to the plb4.6 bus, it says :

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
ERROR:MDT - issued from TCL procedure "check_splb_native_dwidth" line 14
DDR_SDRAM (mpmc) -
DDR_SDRAM::C_SPLB0 has native width set to 32. The bus connected to the port
has width of 64. A 32 bit MPMC port can only be connected to a 32 bit wide
bus.

How can I resolve this issue?

Solution

The native data width (C_MPLB_NATIVE_DWIDTH) of the TFT core is 64. However, the C_SPLBx_NATIVE_DWIDTH parameter of MPMC is assigned as 32 in the MHS file. Changing this parameter to "64"will fix the issue.
AR# 37831
Date Created 09/02/2010
Last Updated 05/19/2012
Status Active
Type Error Message
Tools
  • EDK - 10.1 sp2
  • EDK - 10.1
  • EDK - 10.1 sp1
  • EDK - 10.1 sp3
IP
  • XPS Thin Film Transistor Controller