AR# 37834: 12.x iMPACT - When an encrypted file is loaded in a Platform Flash XL, you cannot load a core file or program the FPGA via JTAG OR JTAG configuration fails when data is loaded in a PROM
12.x iMPACT - When an encrypted file is loaded in a Platform Flash XL, you cannot load a core file or program the FPGA via JTAG OR JTAG configuration fails when data is loaded in a PROM
For an FPGA with a Platform Flash XL attached, when I attempt to program my FPGA in JTAG mode or indirectly program the flash, the operation fails and the following appearsin the console:
INFO:iMPACT:2217 - Error shows in the status register, CRC Error bit is NOT 0. INFO:iMPACT:2218 - Error shows in the status register, release done bit is NOT 1. INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 1011 0000 0011 0000 0000 0011 1100 0000 INFO:iMPACT:579 - '1': Completed downloading bit file to device. INFO:iMPACT:188 - '1': Programming completed successfully. Match_cycle = NoWait. Match cycle: NoWait LCK_cycle = NoWait. LCK cycle: NoWait INFO:iMPACT - '1': Checking done pin....done. '1': Programming terminated. DONE did not go high. PROGRESS_END - End Operation. Elapsed time = 10 sec.
How do I work around this issue?
This message is related to the JTAG algorithm. It occurs when the FPGA is in a Master mode and provides the configuration clock. The JPROG toggles INIT, samples the Mode pins which starts the clock, resulting in some data being clocked in from the Platform Flash XL.
The data clocked in means that the Decryptor enable bit gets set in CTL0; this prevents the unencrypted data from being loaded over JTAG. To prevent this from happening, you can add in another command after the JPROG. This allows the FPGA to be cleared, but means that INIT does not toggle. This can be done in SVF; you need to program using SVF and modify the SVF file. The modification is near the beginning. You need to add an ISC_PROGRAM directly after the JPROGRAM. Following is an example:
// Created using Xilinx Cse Software [ISE - 12.1] // Date: Wed Sep 01 11:41:38 2010
TRST OFF; ENDIR IDLE; ENDDR IDLE; STATE RESET; STATE IDLE; FREQUENCY 1E6 HZ; TIR 0 ; HIR 0 ; TDR 0 ; HDR 0 ; TIR 0 ; HIR 0 ; HDR 0 ; TDR 0 ; TIR 0 ; HIR 0 ; TDR 0 ; HDR 0 ; TIR 0 ; HIR 0 ; TDR 0 ; HDR 0 ; TIR 0 ; HIR 0 ; HDR 0 ; TDR 0 ; //Loading device with 'bypass' instruction. SIR 10 TDI (03ff) SMASK (03ff) ; // Loading device with a `jprogram` instruction. SIR 10 TDI (03cb) ; // Add in the ISC_PROGRAM instruction -1111010001 SIR 10 TDI (03d1);
The recommendation is to create a SVF for erase process and apply the above edit to the SVF file.
With thecurrent version of iMPACT, the process of playing an SVF file might not complete to 100% and stops at 99%.
All the commandsare played correctly and apower-cycle of the board enables further access with iMPACT to program new data using JTAG.
An alternate workaround is to change the Mode pins to JTAG before attempting JTAG programming.