AR# 37875
ML40x - LVDS support on the J5 connector
Description
Does the header J5 on the ML401/402/403 board support differential signaling?Solution
The Expansion Differential Connectors header (J5), on the ML401/402/403 pinout is given in Table 9 of UG080:
The pins of this header connect to the FPGA I/O and can be used as independent single-ended nets as well as differential signaling, with one exception.
Differential pair AD19-AC19 are lower capacitance clock pins that connect to Clock Capable I/Os. These pins do not support LVDS outputs, and become regular user I/Os when not needed for clocks.
When considering how to use the J5 header, it is important to realize that this differential pair does not support LVDS outputs.
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Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 37874 | ML40x - Known Issues and Release Notes Master Answer Record | N/A | N/A |
Associated Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 37874 | ML40x - Known Issues and Release Notes Master Answer Record | N/A | N/A |
| AR# 37875 | |
|---|---|
| Date | 11/12/2018 |
| Status | Active |
| Type | General Article |
| Devices | |
| Boards & Kits | |