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AR# 37903

10.1.03i ChipScope IBERT - IBERT generation fails with "ERROR:Pack:679" during MAP process


IBERT generation fails in MAP process. The IBERT CoreGenerator shows the following message:

* Mapping Design (Step 4 of 6) *

Running: map -intstyle silent -w -ol high -cm speed -o ibert_top.map.ncd ibert_top.ngd
Directory: E:\ct368\hdmi_rx_test22\ibertgtp_temp
Start Time: Tue Aug 17 13:41:44 GMT+08:00 2010

Please wait ............................................................

End Time: Tue Aug 17 13:42:42 GMT+08:00 2010
Step 4 Elapsed Time: 00:00:57
Total Elapsed Time: 00:23:18

* Mapping Design Failed *

When I look into the MAP report located inthe ibertgtp_temp folder under the directory where the IBERT core is generated, I see the following error:
"ERROR:Pack:679 - Unable to obey design constraints (LOC=Y4) which require the combination of the following symbols into a single IPAD component: PAD symbol "CLKIN_P_IPAD&lt;0&gt;" (Pad Signal = CLKIN_P_IPAD&lt;0&gt;) BUF symbol "V5_IBUFDS_GT_RETARGET_ML_IBUF_1" (Output Signal = V5_IBUFDS_GT_RETARGET_ML_IBUF_1_ML_NEW_IP) PAD symbol "DCLK_IPAD<0>" (Pad Signal = DCLK_IPAD<0>) More than one pad symbol.Please correct the design constraints accordingly.

How can I resolve this problem?


The error occurs because the IBERT system clock is incorrectly assigned to the location (Y4 in this case) of the MGT reference clock which results in two clockinputs being packed into the same PAD.
The IBERT system clock requiresa free-running clock on the board whose frequency is 32 MHz to 210 MHz. The MGT reference clock cannot be used as the IBERT system clock. For detailed information of IBERT system clock, please refer tothe ChipScope Pro 10.1 Serial I/O Toolkit User Guide (UG213).
To resolve this problem, change the IBERT system clock location to a PAD where an appropriate clock is connected on theboard.
AR# 37903
Date 12/15/2012
Status Active
Type General Article
  • ChipScope Pro - 10.1
  • ChipScope Pro - 10.1 sp1
  • ChipScope Pro - 10.1 sp2
  • ChipScope Pro - 10.1 sp3