The duty cycle distortion and jitter on the SPI-4.2 source core reference clock input (SysClk) appears on TDClk. Hence, there areseveral requirements and recommendations customers need to follow to ensure the quality of the TDClk.
Jitter requirements It is required that the SysClk has jitter less than 50ps, since any jitter present on the SysClk appears on the TDClk. Duty Cycle Distortion requirements The duty cycle distortion on SysClk also appears on the TDClk clock.There are different duty cycle distortion requirements on SysClk depending on the clocking scheme used to generate the TDClk. MMCM or DCM clocking scheme For MMCM or DCM based designs, the input reference clock (SysClk) duty cycle requirement is 45/55 or tighter. The MMCM or DCM is capable of correcting the duty cycle of the input clock. Regional clocking or PMCD scheme For Regional Clock or PMCD based designs, the input reference clock (SysClk) duty cycle requirement is 48/52 or tighter. The duty cycle requirement for the input reference clock (SysClk) is tighter in a Regional Clock or PMCD based design because the duty cycle distortion for SysClk passes through the BUFIO or PMCD. Placement of Clocking and Output I/O components To further reduce the duty cycle distortion of TDClk, it is strongly recommended that customers place the clocking and I/O output components as close as possible to each other. This placement also reduces clock skew on TDClk which improves the available PCB and system noise budget. For more information, see the SPI-4.2 User Guide available in ISE Design Suite 12.4 and later. Instantiating MMCM using the LogiCore Clocking Wizard (Virtex-6 FPGA only) It is recommended that users utilize the LogiCORE Clocking Wizard IP to generate the optimum MMCM instantiation for their specific data rate; see (Xilinx Answer 39432) for step-by-step guidance on how to generate a MMCM instantiation for the SPI-4.2 core using the Clocking Wizard IP.The Clocking Wizard IP also provides jitter estimates in its summary page and this data can be used to calculate the timing budget of the SPI-4.2 source interface. For more information on calculating the timing budget for the SPI-4.2 source interface, see the SPI-4.2 User Guide available in ISE Design Suite 12.4 and later.