AR# 37937: Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.1
Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.1
This article contains issues resolved in the Virtex-6 FPGA Integrated Block v2.1 Wrapper for PCI Express that are also listed in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.
Synplify flow now supported for entire synthesis / implementation
A script is now provided to synthesize and implement the generated example design with Synplify. The script calls XST to Synthesize the wrapper source code. Synthesis for the wrapper source code is only supported by XST.
Added support for QPro Virtex-6 Hi-Rel devices
Support for all QPro Virtex-6 FPGA Hi-Rel devices has now been enabled.
Added support for ISE Simulator (ISIM)
Support has been enabled for ISE Simulator (ISIM).
8-lane Gen2 product is now supported in the Virtex-6 HXT devices.
Support for 8-lane Gen2 product, in Virtex-6 HXT devices is now available.
GTX Production Settings Updated
GTX settings have been updated per Production GTX settings, based on PCI Express protocol characterization.
GUI support for 8-lane Gen2 configuration
Issue resolved where GUI did not allow generation of an 8-lane Gen2 design for an LX365T-3 device and allowed generation of an 8-lane Gen2 design for a LX550T-2 device, which is not supported.
GUI support for PCIe Block locations for SX315T-FF1156
Issue resolved where the GUI claimed 4 PCIe Block locations available on the SX315T-FF1156, whereas this device only has 2 available PCIe Blocks.
Use of corename "core" in VHDL design causing implementation failure
CR 538681, 569546
Issue resolved where use of corename "core" for a VHDL design caused implementation failures. The use of corename "core_i" is, however, disabled, as this is used as the instance name of the core in the VHDL design.
Updates to improve timing on Root Port configuration
Updates have been made the implementation scripts and delivered UCFs to improve timing on the Root Port configuration design.
Default simulation test has been upgraded
CR 571632, 532234
Default simulation test has been upgraded to include memory and I/O reads and writes.
cfg_msg_* interface ports on Root Port Model now visible
cfg_msg_* ports are now visible at the top level of the Root Port Model delivered with Endpoint product.
cfg_wr_rw1c_as_rw_n port in Root Port product now connected tHard Block
cfg_wr_rw1c_as_rw_n port in the Root Port product is now connected to the port on the Integrated Block for PCI Express.
128-bit wrapper back-pressure on User Interface when Block is full
Issue resolved where the 128-bit wrapper was not back pressuring the User Interface when the Transmit buffers were full, causing data loss.
User non-posted OK signal undriven in VHDL Root Port model
Issue resolved where the User non-posted OK signal was undriven in the VHDL Root Port model, preventing memory read transactions from passing to the User Interface.
Fixed missing default case statement in FSM in 128-bit PIexample design
Issue resolved where the default case statement was missing in the FSM in the 128-bit PIexample design.
Redeclaration of signals in VHDL instantiation template
Issue resolved where the signals were re-declared in the VHDL instantiation template, causing synthesis errors when used.
I/O Write Completion by PIO example design
The PIO example design now generates completions for I/O Writes.
Revision History 01/18/2012 - Modified format to use a single AR for all known issues and referenced 45723 for all known issues. Any issue that was listed here is now in AR 45723. 02/10/2011 - Updated description of resolved issue CR 531976 11/17/2010 - Added 38223,39164 10/11/2010 - Added "AXI" designation to title for doc center. 10/05/2010 - Initial Release