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AR# 37947

Design Assistant for PCI Express - Virtex-6 FPGA Integrated Block Wrapper "ERROR:ConstraintSystem:59 - Constraint "

Description


When I implement the default design generated by theCORE Generator software for the ML605 board, an error similar to the following occurs:
"ERROR:ConstraintSystem:59 - Constraint <INST "core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC = GTXE1_X0Y15;>
[../../example_design/xilinx_pcie_2_0_ep_v6_08_lane_gen1_xc6vlx240t-ff1156-1_ML605.ucf(111)]: INST "core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file."
NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution

Make sure the correct device is selected while creating the CORE Generator project and that ML605 is selected in the GUI while configuring the parameters for core generation.

Revision History:
10/11/2010 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 37947
Date Created 10/13/2010
Last Updated 02/11/2013
Status Active
Type General Article
IP
  • Endpoint Block Wrapper for PCI Express