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AR# 37973

Design Assistant for PCI Express - Virtex-6 Integrated Block "ERROR:Place:1224 - Component-"/pcie_clocking_i/mmcm_adv_i"cannot find any feasible target location during placement"


The following error occurs when implementing a design with Integrated Block for PCI Express:

"ERROR:Place:1224 - Component-"u_pcie_intf/core/pcie_clocking_i/mmcm_adv_i" cannot find any feasible target location during placement."

NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information


TXOUTCLK from GTX is connected to the input of the MMCM. The MMCM and GTX of lane 0 which sources the clock to the MMCM must be in the same clocking region. The error occurs if the user attempts to move the MMCM out of the same region as GTX lane 0. A BUFG cannot be inserted on this path due to the requirements of the GTX delay aligner work-around; for details, see (Xilinx Answer 39456). Starting with the cores released in ISE 13.1 (v2.3 (AXI) and v1.7 (legacy TRN)), the UCF contains placement constraints for the MMCM.

The error message means that the MMCM is in the same clock region as the lane 0 GTX is occupied.

Revision History:

02/24/2011 - Initial release
AR# 37973
Date 02/23/2011
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less
  • Endpoint Block Wrapper for PCI Express
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