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AR# 37976

FIFO Generator v7.2 - Release Notes and Known Issues for ISE 12.3

Description


This Release Notes and Known Issues Answer Record is for the FIFO Generator v7.2 Core, released in ISE12.3 software and contains the following information:
  • General Information
  • New Features
  • Bug Fixes
  • Known Issues
  • Technical Support

General Information
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution


For the most recent updates to the IP installation instructions for this core, see:
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
For software requirements, please go to the "Software Requirements" link on that page.

This file contains Release Notes for the Xilinx LogiCORE IP FIFO Generator v7.2 solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm

New Features in v7.2
  • AXI4 (AXI4-Stream, AXI4 and AXI4-Lite) Support (Spartan-6 and Virtex-6 devices only)
  • ISE 12.3 software support

Bug Fixesin v7.2
  • In the FIFO Generator GUI, navigation buttons at the bottom are not accessible unless the screen resolution is set to 1600x1200 or 1900x1200.
  • CR 568630
  • The FIFO Generator GUI does not generate the core if the depth is reduced after the data count option is selected.
  • CR 570314

Known Issues in v7.2
The following are known issues for v7.2 of this core at thetime of release:
  • In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
  • CR 467240
    (Xilinx Answer 31379)LogiCORE FIFO Generator v4.3 - Cannot change read/write clock frequencies with Built-in FIFO when importing an XCO file
  • The FIFO Generator GUI does not generate the core if the Family is Spartan-6, and FIFO Implementation Type is either Common or Independent Clock Block RAM, and the depth is 64K and the width is 36.
  • CR 570041
    (Xilinx Answer 37201)LogiCORE FIFO Generator 6.3 - Crashes when creating a 36 x65K core

Technical Support
To obtain technical support, create a WebCase at www.xilinx.com/support, Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.
AR# 37976
Date Created 09/24/2010
Last Updated 05/19/2012
Status Active
Type Release Notes
Tools
  • ISE Design Suite - 12.3
IP
  • FIFO Generator