Performance is not the maximum data rate.
The DRAM data bus achieves near peak bandwidth only during bursts of read or write.
Any DRAM data bus overhead will lower the effective data rate.
- Precharge time for changing rows within the same bank (Where the Access address is not in the same row (page hit))
- Write recovery time to change to read accesses
- Bus turnaround time to change from read to write
Efficiency (%) = clock cycles transferring data / total clock cycles.
Effective Bandwidth = Peak Bandwidth * Efficiency
The efficiency of the MCB is highly dependent on the address/traffic pattern in use.
To determine the efficiency for a specific application, it is important to simulate the design with the application's address/traffic pattern.
To get the above clock cycles, you can add counters in the source code.
One counter is used for the total clock cycles and will be enabled by the cal_done signal.
Transferring data cycles can be enabled by either wr_en or rd_en signals.
Wr_en or rd_en can be achieved from cs_n, ras_n, cas_n and we_n signals.
To improve efficiency, you can select the ROW_BANK_COLUMN address mapping scheme for a stream data transaction and BANK_ROW_COLUMN address mapping scheme for a short, random transaction.
9/9/2014 - Initial Release