AR# 38023

FIFO Generator v6.2 - asynchronous reset behavior of FIFO and when can I start to assert write enable and read enable

Description


What is asynchronous reset behavior of FIFO and when can I start to assert write enable and read enable?

Solution


Asynchronous reset behavior:

(Memory Type is Block Ram, Distributed Ram, and Shift RAM)

There are two asynchronous reset behaviors available for FIFO configurations:

  • Full flags reset to 1
  • Full flags reset to 0

The reset requirements and the behavior of the FIFO is different depending on the full flags reset value chosen.
Full flags reset value of 1:

FIFO requires a minimum asynchronous reset pulse of 1 write clock period.

After reset is deasserted, Full flags deassert after 3 clock periods (wr_clk) and the FIFO is now ready for writing.

So wr_en and rd_en cannot be asserted when reset is asserted in order to avoid unexpected behavior.

Full flags reset value of 0:

FIFO requires a minimum asynchronous reset pulse of 1 write clock period.

Wr_en can be asserted approximately three clock cycles after the assertion of asynchronous reset.

Overflow and underflow will be de-asserted after reset.



Asynchronous reset behavior (Memory Type is Built-in FIFO)

Built-In FIFOs require an asynchronous reset pulse of at least 3 read and write clock cycles.

During reset, wr_en and rd_en cannot be asserted.

Wr_en can be asserted after asynchronous reset is released.



AR# 38023
Date 10/21/2014
Status Active
Type General Article
IP