Example of the error - 1. Given a design is a top-level ABEL file for F1.4. Timing simulation & fitter report give wrong results. Functional simualtion works correctly. In the ABEL code, the equation & signals of concern is "ACK=ACKWR # (NB_RD_ACK)(RDCEN)" In the fitter report under the equations section, ACK has a completely different equation. 2. In the ABEL code, ACKN=!ACK (sounds simple enough). But in the fitter report, ACKN=ACKN_BUFR
Solution
This problem is fixed in the latest M1.4 CPLD Tools Update available on the Xilinx Download Area: