How do I control the clock skew calculation through a BUFGMUX?
I have a design withtwo clock going into a BUFGMUX and I would like to control the clock path that is used for the clock skew calculation. The path that is showing a large clock skew is crossing clock domains so the clock skew is propagating to the worst case clock driver. This results in the incorrect input clock to the BUFGMUX to be used, thusresulting in large clock skew.
This is not controlled by the PRIORITY keyword as happens with PERIOD constraint propagation. In order to tell the tools when input clock to the BUFGMUX to use for the clock skew calculation, you should apply a PIN TIG on the other input to the BUFGMUX. An example of the constraint is on page 182 of the constraints guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/cgd.pdf
PIN mod.pin TIG;