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AR# 38100

Project Navigator - How can I simulate the VHDL Wave Generator example design?


I am using the VHDL Arbitrary Programmable Wave Generator with theRS-232 UART Interface example design (wave_gen_vhd_s6/v6). I would like to perform a behavioral simulation, however, I observe that the design does nothave a test bench.
How can I simulate this example design?


A test bench was not provided for the VHDL version of this example design. Development has been notified in order to add a VHDL test bench in a future release of the ISE Design Suite.
To work around this issue, open the Verilog version of this example design and use the test bench files provided from this example in the VHDL design.This allows for a behavioral simulation of the design (assuming your chosen simulator supports mixed-mode simulation).
If your simulator does not support mixed-mode simulation, consider using the Xilinx ISim simulator.
AR# 38100
Date 12/15/2012
Status Active
Type General Article
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
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  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
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