AR# 38105

MIG v3.3, Spartan-3A DDR2 - Failed MAXDELAY constraint on "dqs_int_delay_in" net for XC3S400a-FT256 devices

Description

When implementing a MIG DDR2 design targeting the XC3S400a-FT256 device, the following MIG provided MAXDELAY constraint fails during timing analysis:

Timing constraint: NET "top_00/dqs_int_delay_in" MAXDELAY = 0.517 ns;

Solution

This failure can be safely ignored.

The MAXDELAY value will be increased to 560 ps in version 13.1 of the ISE software.

In the meantime, modify the MAXDELAY value manually to avoid the timing failure.

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
37173	MIG v3.6 - Release Notes and Known Issues for ISE Design Suite 12.3	N/A	N/A

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
38951	MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2	N/A	N/A
37173	MIG v3.6 - Release Notes and Known Issues for ISE Design Suite 12.3	N/A	N/A

AR# 38105
Date	08/12/2014
Status	Active
Type	Known Issues
Devices	Virtex-6 CXT Virtex-6 HXT Virtex-6 LX More Virtex-6 LXT Virtex-6 SXT Less
IP	MIG

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