General Description: PAR will sometimes duplicate flops to drive separate sections of a net. This is considered to be an "output-to-output route-thru." This can be a problem when the input net is asynchronous, as there is a chance that the flip-flops will be clocked while the input is changing, and the two FFs could end up in different states.
This issue affects all 4000-derivative parts, including Spartan and Spartan-XL.
The following Perl script can be used to detect occurrences of duplicated registers in XC4000X* designs. The routed .ncd file is used as a command line argument. A valid Xilinx environment must be present for the script to run successfully. It may be necessary to modify the first line to the correct location, perl5, on your system.
NOTE: It has been found that this script does not give accurate results for cases where CLBs contains multiple route-thrus. A patch for XDL is available to correct. this. See (Xilinx Answer 13636) for details.
Sample output: swissx  dup_flop.pl test.ncd
A register has been replicated for net "DONE", which is driven by CLB "ACTIVE_N" at site CLB_R9C14:
print "\n"; print "A register has been replicated for net $net_name,\n"; print "which is driven by CLB $comp_name at site $site_name.\n"; print "\n";
An environment variable (CM_EXCLUDE_XQYQ) has been created that disables the use of CLB flip-flop outputs for output-to-output route-thrus.
To set the variable:
Workstations: setenv CM_EXCLUDE_XQYQ
PCs: set CM_EXCLUDE_XQYQ=TRUE
The replication can be prevented for a specific flip-flop by using mapping constraints (BLKNM, RLOC, etc.) to ensure that the FF is always packed into a CLB with another FF. The replication can not occur if there is not an unused FF bel in the CLB. This work-around is preferable to the environment variable work because it does not prevent replication of all flip-flops, but just the critical ones.