For the Virtex-6 FPGA MMCM, when CLKINPFD <= 135 MHz, the BANDWIDTH must be set to LOW.
There is a requirement for Virtex-6 FPGA designs using MMCMs with a CLKINPFD of less than or equal to 135 MHz, where the BANDWIDTH attribute must always be set to LOW. CLKINPFD is the input clock frequency at the Phase Frequency Detector and is calculated as (Fclkin/D) or (1000/[CLKINn_PERIOD * DIVCLK_DIVIDE]).
In 12.3 ISE Design Suite and previous design tools, when BANDWIDTH = OPTIMIZED, the software defaults to HIGH and must be manually changed to LOW in these cases. The ISE design tools and affected IP are scheduled to be fixed in version 12.4 so that BANDWIDTH = OPTIMIZED will be set to LOW and the affected IP set BANDWIDTH = LOW when CLKINPFD <= 135 MHz.
When CLKINPFD > 135 MHz, OPTIMIZED will remain unchanged.
Any affected design should be re-implemented from MAP (or earlier) in ISE version 12.4 or later.
If the design cannot be re-implemented in ISE 12.4 or later, use the following work-around: Directly change the MMCM bandwidth settings within FPGA Editor, re-run timing analysis, and regenerate the bitstream.
Please note that MMCMs with LOW bandwidth and HIGH bandwidth have different phase errors that might affect system performance. Phase error is reported by the Clocking Wizard as well as in timing analysis. Because of this difference in phase error, when switching from HIGH or OPTIMIZED to LOW bandwidth, designs where phase alignment between the input and output of the MMCM is important should be checked to ensure all timing constraints are still met (i.e., OFFSET IN, OFFSET OUT). See Figure 1.
For example, assuming an input clock frequency of 135 MHz using an MMCM with a VCO of 810 MHz, where CLKFBOUT_MULT_F = 6, DIVCLK_DIVIDE = 1 and CLKOUT0_DIVIDE_F = 6, the clock uncertainty calculated during timing anaylsis of an OFFSET constraint is:
HIGH Bandwidth: Clock Uncertainty: 0.172ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.121ns Phase Error (PE): 0.106ns
LOW Bandwidth: Clock Uncertainty: 0.386ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.121ns Phase Error (PE): 0.320ns
Many designs might not be affected. Designs where phase alignment does not affect system performance will not be affected. For example, logic clocked by the outputs from a single MMCM as shown in figure 2 will not be affected.
Phase error does not affect the clock uncertainty calculation:
High Bandwidth & Low Bandwidth Clock Uncertainty: 0.070ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.121ns Phase Error (PE): 0.000ns