AR# 38133: Virtex-6 FPGA MMCM Design Advisory - Restriction for DIVCLK_DIVIDE value when Fclkin > 315 MHz
Virtex-6 FPGA MMCM Design Advisory - Restriction for DIVCLK_DIVIDE value when Fclkin > 315 MHz
In Virtex-6 FPGA designs with an MMCM input clock (Fclkin) greater than 315 MHz, DIVCLK_DIVIDE (input divider) values of 3 and 4 must not be used.
The workaround for designs with Fclkin> 315 MHz using a DIVCLK_DIVIDE setting of 3 or 4 is to multiply-up the DIVCLK_DIVIDE and CLKFBOUT_MULT_F values in order to maintain the same CLKIN, VCO, and CLKOUT frequencies. See the example below. Attribute changes require re-generation of the bitstream.