UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 38133

Virtex-6 FPGA MMCM Design Advisory - Restriction for DIVCLK_DIVIDE value when Fclkin > 315 MHz

Description

In Virtex-6 FPGA designs with an MMCM input clock (Fclkin) greater than 315 MHz, DIVCLK_DIVIDE (input divider) values of 3 and 4 must not be used.

Solution

The workaround for designs with Fclkin> 315 MHz using a DIVCLK_DIVIDE setting of 3 or 4 is to multiply-up the DIVCLK_DIVIDE and CLKFBOUT_MULT_F values in order to maintain the same CLKIN, VCO, and CLKOUT frequencies. See the example below. Attribute changes require re-generation of the bitstream.


Example:

In a design where the MMCM:

CLKIN = 400 MHz
DIVCLK_DIVIDE = 3
CLKFBOUT_MULT = 6

The values can be changed to:

DIVCLK_DIVIDE = 6
CLKFBOUT_MULT = 12


A DRC error will occur in designs with DIVCLK_DIVIDE = 3 or 4 starting in ISE 12.4.
The following cores are affected by this restriction:
  • Aurora 64B66B - fixed in v1.5 released with ISE 12.4
  • Virtex-6 GTX Wizard - fixed in v1.8 released with ISE 12.4
  • SPI-4.2/SPI-4.2 Lite - fixed in a future version
  • Clocking Wizard - fixed in ISE 12.4
AR# 38133
Date Created 09/20/2010
Last Updated 10/12/2010
Status Active
Type Design Advisory
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less