AR# 38174: 12.2 EDK, MPMC 6.01a - "WARNING:Route:436 - The router has detected an unroutable situation..."
12.2 EDK, MPMC 6.01a - "WARNING:Route:436 - The router has detected an unroutable situation..."
When I attempt to route my Spartan-6 MPMC design in EDK, the following warning occurs which does not allow the design to finish routing:
"Phase 2 : 43872 unrouted; REAL time: 36 secs WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections: Unroutable signal: Dcm_all_locked pin: MPMC_0/mpmc_core_0/gen_spartan6_mcb.gen_spartan6_bufpll_mcb.bufpll_0/LOCKED"
This warning can occur in two scenarios:
When the tools place the PLL instance in a location where the global clock routing cannot be accessed. This prevents the tools from routing the signals to the proper buffers and causes the failure. Manually constraining the PLL instance to a different location should help to resolve the issue. Following is an example constraint:
This specific constraint will be different depending on the design. This issue was tested in 12.3 and there were no warning messages in the design.
When using multiple resources in the Clock Generator block (e.g., DCM and PLL both configured within the Clock Generator). The Clock Generator then produces a LOCKED signal output which is the DCM_LOCKED signal ANDed with the PLL_LOCKED signal. However, when using the MPMC block in a Spartan-6 device, it is unroutable to connect this combined CLK_GEN_LOCKED signal to the MPMC input LOCKED pin because the MPMC for the Spartan-6 device must use the BUFPLL_MCB which has to connect to the PLL_LOCKED signal directly, or else the unroutable situation described above can occur. This is a hardware limitation in Spartan-6 FPGA. To work around this issue, it is necessary to split the DCM and PLL clocking configurations into two Clock Generator cores; and as such, use two Clock Management Tiles on the device. This ultimately allows the PLL_LOCKED signal to be output directly from the Clock Generator instance 1 block into the MPMC and connect directly to the BUFPLL_MCB. CRs have been filed to help identify this issue by enhancing the message from the Router and also improving the documentation.