GENERAL DESCRIPTION: Excess logic can get stripped from a design if a customer uses I/O terminals to define top-level I/O on a schematic rather than using IPADs and OPADs from the Xilinx Unified Libraries.
The stripping actually only occurs on the clock buffers. In the trimming section of the Map Report the clocks will be defined as sourceless.
This occurs because ngdbuild will automatically insert IPADs in front of IBUFs, even if these IPADs do not exist in the EDIF netlist.
The resolution is to always use IPADs and OPADs, and not I/O terminals to represent the pins of a Xilinx device. I/O terminals should ONLY be used to make connections between levels of hierarchy.
Note: In F1.5, I/O terminals have been renamed to Hierarchy Connectors to help alleviate inappropriate use of them.