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AR# 38220

FIFO Generator - Why is the Clock Enable signal CKE not available in FIFO generator core?


Why isthere not a port forCKE signal in the FIFO Generator Core? How do I controlrd_clk and wr_clk?


For proper functioning of the FIFO generator core, theFIFOrd_clk and wr_clk should befree running.

The reason is that theStatus flags (empty, full, Almost Full, Almost Empty,Programmable Full,Programmable empty) will not give the true status of the FIFO for controlled rd_clk and wr_clk by CKE, or any other means. In UG175, it states on page 97:

The FIFO Generator is designed to work only with free-running write and read clocks. Xilinx does not recommend controlling the core by manipulating RD_CLK and WR_CLK. If this functionality is required to gate FIFO operation, we recommend using the write enable (WR_EN) and read enable (RD_EN) signals.

If application requiresa gated FIFO operation,we recommend controllingthe core by using the write enable
(WR_EN) and read enable (RD_EN) signals as stated in UG175.
AR# 38220
Date 01/21/2013
Status Active
Type General Article
  • ISE - 10.1
  • ISE Design Suite - 11.1
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  • ISE Design Suite - 11.3
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  • FIFO Generator
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