AR# 38283


Virtex-6 FPGA GTH Transceiver: ES HXT operating recommendations


This answer record contains descriptions and the implications to user applications of the issues noted in the Virtex-6 ES Errata that pertain to the GTH transceiver.


Supported PCB Trace Characteristics

The GTH transceiver is currently restricted to short-reach applications with a PCB trace of up to 8 inches or less of FR-4. The recommended near end transmit signal swing should be between 370 mVppd and 770 mVppd for best jitter performance. Backplane applications are currently not supported.

Use the following attributes to set Transmitter swing and emphasis.

Amplitude (Swing): TX_CFG0_LANE<n>
Post-Cursor Emphasis: TX_PREEMPH_LANE<n>
Pre-Cursor Emphasis: TX_PREEMPH_LANE<n>

Use the following attributes to set Receiver AGC, CTLE, and DFE.


The recommended settings for these attributes can be found in Answer Record 37414.

Refer to UG371: Virtex-6 FPGA GTH Transceivers User Guide for additional information regarding these attributes.

T_BLOCK_TYPE Misclassification in 10 Gigabit Ethernet 64B/66B Mode

The 10 Gigabit Ethernet specification indicates the following:

T_BLOCK_TYPE will = C when:

a) ...
b) 'one valid ordered set and four valid control characters other than /O/, /S/ and /T/'

ES HXT silicon behaves slightly differently:

a) ...
b) 'one valid ordered set and four valid control characters other than /E/, /O/, /S/ and /T/'

This behavior will only occur when a 64 bit XGMII TX word contains an ordered sequence/signal in one half and has one or more /E/ bytes in the other half of the word. This is avoidable at a user application level while still operating within the 10 Gigabit Ethernet specification and the Xilinx 10GBASE-R core works correctly without encountering this problem.

GTH TXUSERCLKOUT and RXUSERCLKOUT in 10 Gigabit Ethernet 64B/66B Mode

The duty cycle of TXUSERCLKOUT and RXUSERCLKOUT is less than 30% when the GTH transceiver is configured in 10 Gigabit Ethernet 64B/66B mode. TXUSERCLKOUT or RXUSERCLKOUT must only be used with the positive clock edge for fabric logic.

Additional Notes for ES Silicon:

(Xilinx Answer 37763) Virtex-6 FPGA GTH Transceivers: AC-JTAG, 1149.6 design considerations

(Xilinx Answer 37412) Virtex-6 FPGA GTH Transceiver: Initialization sequence for ES silicon

(Xilinx Answer 37414) Virtex-6 FPGA GTH Transceiver: Attribute updates for ES silicon
AR# 38283
Date 12/15/2012
Status Active
Type General Article
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