This answer record identifies starting points when debugging simulation related issues to the Virtex-4/Virtex-5/Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC.
Note: This Answer Record is a part of the Ethernet IP Solution Center (Xilinx Answer 38279).The Xilinx Solution Center for Ethernet IP is available to address all questions related to Ethernet IP. Whether you are starting a new design with Ethernet IP cores or troubleshooting a problem, use the Solution Center for Ethernet IP to guide you to the right information.
The Example Design provided when the Embedded Tri-Mode Ethernet MAC Wrapper is generated by Core Generator contains an example simulation testbench and scripts to get started. See Simulating the TEMAC Wrapper Example Design in the Embedded TEMAC Wrapper Getting Started Guide for more details.
The Debugging Designs Chapter at the end of the Virtex-6 and Virtex-5 FPGA Embedded TEMAC Wrapper Getting Started Guide has a Simulation Debug section with further tips on debugging Simulation setup and licensing, library compilation, and link bring up.