AR# 38319

Design Assistant for V4/V5/V6 FPGA Embedded Tri-Mode Ethernet MAC - Hardware Debug and Link Bring up

Description

This answer record identifies starting points when debugging hardware and link bring up issues to the Virtex-4/Virtex-5/Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC.

Note: This Answer Record is a part of the Ethernet IP Solution Center (Xilinx Answer 38279).The Xilinx Solution Center for Ethernet IP is available to address all questions related to Ethernet IP. Whether you are starting a new design with Ethernet IP cores or troubleshooting a problem, use the Ethernet IP Solution Center to guide you to the right information.

Solution

The Debugging Designs Chapter at the end of the Virtex-6 and Virtex-5 FPGA Embedded TEMAC Wrapper Getting Started Guide has a Hardware debug section with guidance on:

General Checks for Hardware Debug
Debugging Problems with Transmitting and Receiving Frames
Link Bring Up Using 1000BASE-X or SGMII
Problems with the MDIO
Configuring the Ethernet MAC to the Correct Speed

The Getting Started Guides are available at the below links:
http://www.xilinx.com/support/documentation/ip_documentation/v6_emac_gsg545.pdf
http://www.xilinx.com/support/documentation/ip_documentation/v5_emac_gsg340.pdf

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
38279	Ethernet IP Solution Center	N/A	N/A

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
38281	Ethernet IP Solution Center - Virtex-4/-5/-6 FPGA Embedded Tri-Mode Ethernet MAC Design Assistant	N/A	N/A

AR# 38319
Date	01/23/2013
Status	Active
Type	General Article
Devices	Virtex-4 FX Virtex-5 FXT Virtex-5 LXT More Virtex-5 SXT Virtex-6 LXT Virtex-6 SXT Less
IP	Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper Virtex-4 Tri-Mode Ethernet Media Access Controller

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