AR# 38334

BPI Configuration Interface Needs Data on Every A<0> Cycle - A<0> Must be Connected to LSB of Address Bus

Description

The BPI interface in the Xilinx FPGA devices expects data on every CCLK cycle. This can lead to potential problems when using a standard 16-bit BPI interface. Note that you must always connect an A<0> to the flash addresses.

Solution

A general 16-bit BPI interface does not use the A<0> pin to address the flash memory. This allows forword addressing instead of byte addressing in 16-bit mode. If you use word addressing,it conflicts with the FPGA BPI configuration interface.

The FPGA BPI interface requires data on every CCLK cycle, and, therefore, with every A<0> cycle. If A<0> is not connected and A<1> is the least significant bit of the address bus,each word will be read twice.

The next table illustrates this point:

CCLK cycle	FPGA Address bus Output FPGA_A[20:0]	Flash Address bus Input Flash_A[19:0] (FPGA_A[20:1])	Flash returns the following data (bitstream) word
0	21'b00...0000	20'b00...000	Data word[0]
1	21'b00...0001	20'b00...000	Data word[0]
2	21'b00...0010	20'b00...001	Data word[1]
3	21'b00...0011	20'b00...001	Data word[1]
...	...	...	...

This is why A<0> must always be connected to theleast significant bitof the data bus.

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AR# 38334
Date	12/15/2012
Status	Active
Type	General Article
Devices	Spartan-3A Spartan-6 LX Spartan-6 LXT More Virtex-5 LX Virtex-5 FXT Virtex-5 LXT Virtex-5 SXT Virtex-5 TXT Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-7 Virtex-7 HT Less

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