CCLK cycle | FPGA Address bus Output FPGA_A[20:0] | Flash Address bus Input Flash_A[19:0] (FPGA_A[20:1]) | Flash returns the following data (bitstream) word |
0 | 21'b00...0000 | 20'b00...000 | Data word[0] |
1 | 21'b00...0001 | 20'b00...000 | Data word[0] |
2 | 21'b00...0010 | 20'b00...001 | Data word[1] |
3 | 21'b00...0011 | 20'b00...001 | Data word[1] |
... | ... | ... | ... |