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AR# 38366

Virtex-6 GTX ES Devices - Glitches in TXOUTCLK


There are glitches observed in TXOUTCLK when the Delay Aligner is used.
This can happen in ES Silicon when TXBUFFER is bypassed and phase alignment is thus needed. After performing Phase Alignment, TXDLYALIGNDISABLE is de-asserted. By de-asserting TXDLYALIGNDISABLE, TXOUTCLK in some cases hasa glitch or is phase-shifted. This behavior can also cause the MMCM driven by TXOUTCLK to lose lock and can cause timing violations in the fabric logic.


In ES Devices toggling TXDLYALIGNDISABLE causes a reset to the delay line. When the delay line is thrown into reset by high TXDLYALIGNDISABLE, a deformation of the output clock can result as the delay line suddenly reverts to its midpoint value. Another deformation can occur when TXDLYALIGNDISABLE drops and the delay line returns to the value that was frozen in the Delay Aligner FSM. Thus, toggling TXDLYALIGNDISABLE results in possible glitches on TXOUTCLK when the delay line is used (POWER_SAVE[4]=0).
The problem has been fixed in Production Devices. In Production Devices, when the TXDLYALIGNDISABLE is asserted the delay line is frozen and it does not revert to midpoint condition.
AR# 38366
Date 05/19/2012
Status Active
Type Known Issues
  • Virtex-6 LXT
  • Virtex-6 SXT
  • XAUI
  • CPRI