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AR# 38384

10/100/1000Mbps Soft Logic Ethernet IP Design Assistant - Synthesis and Implementation


This Answer Record identifies starting points when debugging synthesis and implementation related issues to the 10/100/1000Mbps Soft Logic Ethernet IP.This includes the Tri-Mode Ethernet MAC core, 1000BASE-X PCS/PMA or SGMII core, and Ethernet Statistics core.

NOTE: This Answer Record is part of the Ethernet IP Solution Center (Xilinx Answer 38279).The Xilinx Solution Center for Ethernet IP is available to address all questions related to Ethernet IP. Whether you are starting a new design with Ethernet IP cores or troubleshooting a problem, use the Solution Center for Ethernet IP to guide you to the right information.


The example design generated with each core in the CORE Generator software comes complete with implementation scripts and UCF constraints files. For more details on using these scripts, see the Implementing your Design section of the Users Guide. If implementation or timing errors are encountered, it is recommended to first try running the example design to see if the failures occur there. If the failures do not exist in the example design, then differences between the example design and the design in which failures are seen can be compared.
The guides are available at the following links:

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
38279 Ethernet IP Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38349 Ethernet IP Solution Center - 10/100/1000Mbps Soft Logic Ethernet IP Design Assistant N/A N/A
AR# 38384
Date 12/15/2012
Status Active
Type General Article
Devices More Less
IP More Less
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