AR# 38387

10/100/1000Mbps Soft Logic Ethernet IP Design Assistant - Hardware Debug and Link bring up

Description

This answer record identifies starting points when debugging hardware and link bring up issues with the 10/100/1000Mbps Ethernet IP.

This is included the Tri-Mode Ethernet MAC core, 1000BASE-X PCS/PMA or SGMII core, and Ethernet Statistics core.

Note: this Answer Record is a part of the Ethernet IP Xilinx Solution Center (Xilinx Answer 38279).

The Xilinx Solution Center for Ethernet IP is available to address all questions related to Ethernet IP.

Whether you are starting a new design with Ethernet IP cores or troubleshooting a problem, use the Solution Center for Ethernet IP to guide you to the right information.

Solution

The Debug Guide at the end of the 1000Base-X PCS/PMA or SGMII Users Guide has a Hardware debug section with guidance on:

General Checks for Hardware Debug
Problems with the MDIO
Problems with Data Reception or Transmission
Problems with Auto-Negotiation
Problems in Obtaining a Link (Auto-Negotiation Disabled)
Problems with a High Bit Error Rate

The User Guide is available at the below link:
http://www.xilinx.com/support/documentation/ip_documentation/gig_eth_pcs_pma_ug155.pdf

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
38279	Ethernet IP Solution Center	N/A	N/A

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
38349	Ethernet IP Solution Center - 10/100/1000Mbps Soft Logic Ethernet IP Design Assistant	N/A	N/A

AR# 38387
Date	09/03/2019
Status	Active
Type	General Article
Devices	Virtex-4 LX Virtex-4 SX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SXT Virtex-5 TXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT More Less
IP	Ethernet 1000BASE-X PCS/PMA or SGMII Ethernet AVB Ethernet Statistics Tri-Mode Ethernet MAC More Less

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