AR# 38400

SPI-4.2 v10.2 - Reduced performance of Virtex-6 FPGA Source core with global clocking when the receiver Sink core is configured with dynamic phase alignment

Description

For Virtex-6 FPGAs, reduced performance is required for the Source core with global clocking when the receiver Sink core is configured with dynamic phase alignment.

Solution

The new limits are:
- 900 Mbps for -1 and -2 speed grades
- 1 Gbps for -3 speed grades

The SPI-4.2 GUI has been updated starting in v10.2rev1 of the core. Instead of using global clocking, regional clocking is recommended for higher performance. Below is a table with all of the performance numbers for Virtex-6 Source core with dynamic phase alignment:



The SPI-4.2 v10.2 rev1 patch is available for download in (Xilinx Answer 38211).
AR# 38400
Date 05/23/2014
Status Archive
Type General Article
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