AR# 38447: Design Assistant for PCI Express - Memory reads result in 0xFFFFFFFF
Design Assistant for PCI Express - Memory reads result in 0xFFFFFFFF
The core is correctly detected by they system but memory read accesses returns 0xffffffff.
Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.
Usually the system will report all 1's for a read if some type of error condition occurs. On a memory read this could be either that the memory enable bit in the command register is not set or, more likely, there was a BAR miss. Both of these will cause the endpoint to return a completion with UR status which will be reported back to the application as all 1's.
Specifically, if using the Endpoint Block Plus core for PCI Express, this may happen if the user has incorrectly tied the cfg_rd_en_n signal to ground, which is the asserted state, or left it floating in the RTL, which means synthesis probably tied it off the ground. By doing this, the user is inadvertently preventing the block plus wrapper from obtaining the information it needs from the block to perform BAR decodes, which will result in BAR misses.