An issue has been seen with an IFD and BUFG in a simple testcase to match the description of Table 91 of Virtex-5 Data Sheet (DS202). Pack uses the IDELAY as a route-thru instead of fully utilizing the IDELAY. The route-thru has more delay than the "Default" IDELAY value, which causes the timing analysis to not match the data sheet (DS202; Table91). This is a known issue and the workaround is to instantiate the IDELAY component with the DEFAULT delay set. Once the IDELAY is fully instantiated, then the timing analysis does match the data sheet. An alternate workaround could be to use IODELAY=BOTH constraint in the ucf.