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  3. AR# 38495: LogiCORE IP Video On Screen Display v1.0 - Why is the layer control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6?

AR# 38495

LogiCORE IP Video On Screen Display v1.0 - Why is the layer control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6?

Description

Why is the layer control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA?

Solution

This is a known problem that only affects the pCore interface and is addressed in the next release of the Video On Screen Display IP. 

This problem has been fixed in the Video On Screen Display 1.0 rev1 patch. See (Xilinx Answer 35635) to obtain the patch.

Please see (Xilinx Answer 33257) for a detailed list of LogiCORE IP Video On Screen Display Release Notes and Known Issues.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33257 LogiCORE IP Video On Screen Display (OSD) - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33257 LogiCORE IP Video On Screen Display (OSD) - Release Notes and Known Issues N/A N/A
AR# 38495
Date 05/26/2014
Status Archive
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Spartan-6 LX
  • Spartan-6 LXT
  • Less
IP
  • On-Screen Display
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