AR# 38506


Virtex-6 FPGA GTX Transceiver - Reference clock phase noise mask


The quality of the reference clock supplied to the RXPLL or TXPLL in the Virtex-6 GTX Transceiver can greatly impact the performance of the transmit jitter and receive jitter tolerance. Jitter or phase noise from the reference clockplays an important roll indetermining this performance; phase noise being the preferred specification method as it allows the designer to incorporate thevarious frequency components that a time based jitter specification might overlook.

This Answer Record contains the reference clock phase noise limits that Xilinx recommends based on the PLL settings being used.


Depending on the reference clock being used, a different mask needs to be applied.The table belowdescribes the points of a mask above which the reference clock phase noise should not exceed.If a reference clock does exceed these masks, it results in additional jitter on TX data.

Phase Noise Limits in dBc/Hz:

Ref ClkFrequency (MHz) 10KHz 100KHz 1MHz 10MHz 20MHz 30MHz 40MHz
100 -126 -128 -130 -135 -136 -140 -144
125 -121 -132 -131 -136 -138 -141 -144
156.25 -119 -130 -130 -135 -136 -140 -143
250 -113 -126 -131 -134 -135 -135 -146
312.5 -110 -125 -132 -135 -135 -135 -135

NOTE: If your desired reference clock rate is not listed in the table above, please use the phase noise mask for the nearest reference clock frequency.
AR# 38506
Date 03/05/2013
Status Active
Type General Article
Devices More Less
People Also Viewed