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AR# 38542

Design Assistant for PCI Express - How to Calculate the Latency of a Packet Presented on the TRN Interface

Description

How can I measure latency of my TLPs through the block?

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe.Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution

The latency through the TRN interface will depend on the following:

  • Traffic pattern
  • Streaming mode operation
  • Number of Lanes
  • Interface Frequency
  • Flow Control

For this reason, to get the most accurate latency numbers, it is best to simulate the core under your expected conditions and your core configuration. It is best to pull the following three signals into your simulation:

  • trn_tsof_n
  • Transceiver's TX DATA bus.
  • Transceiver's TX CHARISK bus

Measure the time between the assertion of trn_tsof_n and when the "Start TLP" Special Character is shown on the TXDATA of the transceiver. Usually, it will be on lane 0 or for an x8 link it can be on lane 0 or lane 4.The "Start TLP" Special Character is K27.7 = 0xFB.CHARISK will assert at this time indicating the 0xFB K character.

Revision History
7/30/2011 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36049 Design Assistant for PCI Express - TRN User Application Interface Questions N/A N/A
AR# 38542
Date Created 07/29/2011
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )