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AR# 38547

Virtex-5 Architecture Wizard - Out of range PFD allowed, resulting in DRC error

Description

The Virtex-5 Architecture Wizard allows PLL values that violate the minimum or maximum Phase Frequency Detector (PFD) input frequency. This causes a DRC error or warning to be issued by the implementation tools.

Solution

Example:

Architecture Wizard is used to generate a PLL with the following values:

CLKIN1_PERIOD = 20.000
CLKOUT0_DIVIDE = 25
DIVCLK_DIVIDE = 5
CLKFBOUT_MULT = 47
REF_JITTER = 0.005000

Architecture Wizard incorrectly allows generation of this configuration.

During implementation, a DRC error or warning will occur:

WARNING:PhysDesignRules:2236 - The DIVCLK_DIVIDE value 5 of PLL_ADV instance
Clocking/clk18p8/PLL_ADV_INST is above the Fin / Fpfd value 2.631579, where
Fin is the input frequency, 50.000000 MHz, and Fpfd min - max values of
19.000000 - 450.000000 MHz.

The valid ranges at the phase frequency detector are between 19 MHz and 450 MHz (Fpfdmin and Fpfdmax).

The 2.613579 comes from the input rate of 50 MHz divided by the 19 Mhz. The DRC message is valid.

Workaround:

Use valid DIVCLK_DIVIDE values such that the Fpfdmin and Fpfdmax specifications from the Virtex-5 FPGA Data Sheet are not violated.

http://www.xilinx.com/support/documentation/virtex-5.htm
AR# 38547
Date Created 10/11/2010
Last Updated 10/22/2010
Status Active
Type Known Issues
Devices
  • Virtex-5 LX
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Less
Tools
  • ISE Design Suite - 12.2
IP
  • PLL Module