AR# 38564

HSSIO - Variation in Analog Power Supply Voltage while Powering up or down Transceivers


When some HSSIO transceivers are powered up or down, variations will be seen on the serial transceiver analog voltage supplies.

If this happens during operation, adjacent operating transceivers will have a reduced margin because of this variation.

The power supply voltage regulator must maintain a constant output voltage even with variations in the load current.

When a serial transceiver is powered up or down, a step change in the power supply load current occurs. 

As a result of this current change, the voltage regulator must adjust to the load change and the resulting variation in the IR drop in the power distribution network.

The response time of a typical voltage regulator depends on the amount of output capacitance on the voltage regulator and the operating frequency of the power supply regulator. 

Typically, the response time is on the order of 10's or 100's of microseconds.

Powering up or down the GT transceiver causes a load current change, and during this time the power supply voltage will vary.

While this is occurring, the adjacent operating GT transceivers will have a reduced margin.

During JTAG reprogramming all GTs are powered down together.

This causes a positive peak in the voltage level


The work-around for this is to not power up or power down all of the transceivers simultaneously, but instead for them to be staggered.
When transceivers are in operation, assert/deassert the transmit side PD and receiver side PD only for one transceiver at a time with intervals of 100 us.

The GT resets signals should also be staggered, in particular those resets affecting the PLLs.

When the PROG_B signal is pulsed, a drop in the current request is expected and this causes a positive peak in the voltage level.

Depending on the power regulators and the number of simultaneously running GT, the peak could exceed the Absolute Maximum Ratings.

When a non-supported voltage peak in the power supply is possible, a staggered power down is recommended before the PROG_B assertion (before JTAG reprogramming of the FPGA).    

AR# 38564
Date 12/18/2014
Status Active
Type General Article
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